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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 3 1 publication order number: ncp81074/d ncp81074a, ncp81074b single channel 10a high speed low-side mosfet driver the ncp81074 is a single channel , low?side mosfet driver. it is capable of providing large peak currents into capacitive loads. this driver can deliver a 7 a peak current at the miller plateau region to help reduce the miller effect during mosfets switching transitions . it exhibits a split output configuration allowing the user to control the turn on and turn off slew rates. this part is available in soic?8 and dfn8 2x2 mm packages. features ? high current drive capability 10 a ? ttl/cmos compatible inputs independent of supply voltage ? high reverse current capability (10 a) peak ? 4 ns typical rise and 4 ns typical fall times with 1.8 nf load ? fast propagation delay times of 15 ns with input falling and 15 ns with input rising ? input voltage range from 4.5 v to 2 0 v ? split output configuration ? dual input design offering drive flexibility ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? server power ? telecommunication, datacenter power ? synchronous rectifier ? switch mode power supply ? dc/dc converter ? power factor correction ? motor drive ? renewable energy, solar inverter dfn8 mn suffix case 506aa marking diagrams xxm 1 1 xxxxxx ayww 1 8 soic?8 case 751 1 8 xxxxxx = specific device code a = assembly location y = year ww = work week = pb?free package see detailed ordering, marking and shipping information on page 2 of this data sheet. ordering information www. onsemi.com xx = specific device code m = date code = pb?free device (note: microdot may be in either location)
ncp81074a, ncp81074b www. onsemi.com 2 ordering information device temperature range ( c) marking input type package type shipping ? ncp81074amntbg ?40 to +140 cl fixed digital threshold dfn8 2x2 (pb?free) 3000 / tape & reel ncp81074bmntbg ?40 to +140 cm vdd based threshold dfn8 2x2 (pb?free) 3000 / tape & reel NCP81074ADR2G ?40 to +140 ncp81074a fixed digital threshold soic?8 (pb?free) 2500 / tape & reel ncp81074bdr2g ?40 to +140 ncp81074b vdd based threshold soic?8 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. block diagram figure 1. ncp81074 block diagram
ncp81074a, ncp81074b www. onsemi.com 3 pin description pin no. symbol description 1 in+ non?inverting input which has logic compatible threshold and hysteresis. if not used, this pin should be connected to either vdd or gnd. it should not be left unconnected. 2 gnd common ground. this ground should be connected very closely to the source of the power mosfet. 3 gnd common ground. this ground should be connected very closely to the source of the power mosfet. 4 outl sink pin. connect to gate of mosfet. 5 outh source pin. connect to gate of mosfet. 6 vdd power supply input pin. 7 vdd power supply input pin. 8 in? inverting input which has logic compatible threshold and hysteresis. if not used, this pin should be connect- ed to either vdd or gnd. it should not be left unconnected figure 2. typical application circuit absolute maximum ratings parameter value unit min max supply voltage vdd ?0.3 24 v output current (dc) iout_dc 0.6 a reverse current (pulse<1 s) 10 a output current (pulse<0.5 s) iout_pulse 10 a input voltage in+, in? ?6 24 v output voltages outh, outl ?0.3 vdd + 0.3 v output voltages (pulse<0.5 s) outh, outl ?3.0 vdd + 3.0 v junction operation temperature t j ?40 150 c storage temperature t stg ?65 160 electrostatic discharge human body model, hbm 4000 v charge device model, cdm 1000 out latch?up protection 500 ma moisture sensitivity level (msl) msl1 stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
ncp81074a, ncp81074b www. onsemi.com 4 recommended operating conditions parameter rating unit vdd supply voltage 4.5 to 20 v in+, in? input voltages ?5 to 20 v junction temperature range ?40 to +140 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 1. thermal information package theta ja ( c/w) theta jc ( c/w) dfn?8 2x2 80.3 11.9 soic?8 115 50 table 2. electrical characteristics (note 1) (typical values: v dd =12v, 1uf from vdd to gnd,ta = tj = ?40 c to 140 c, typical at t amb = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit supply voltage vdd under voltage lockout (rising) v ccr vdd rising 3.7 3.9 4.1 v vdd under voltage lockout (falling) v ccf vdd falling 3.4 3.6 3.8 v vdd under voltage lockout (hysteresis) v cch 300 mv operating current (no switching) i dd 1.2 2 ma vdd under voltage lockout to output delay (note 1) vdd rising 10 s inputs ncp81074a high threshold v thh input rising from logic low 1.9 2.1 2.3 v ncp81074a low threshold v thl input falling from logic high 1.1 1.3 1.5 v vin_hys input signal hysteresis 0.8 v ncp81074b high threshold v thh input rising from logic low (vdd = 8 v to 12 v) vdd ?3.5 vdd ?3.1 vdd ?2.7 v ncp81074b low threshold v thl input falling from logic high (vdd = 8 v to 12 v) gnd +2.6 gnd +2.9 gnd +3.2 v in? pull?up resistor r in? 200 k in+ pull?down resistor r in+ 200 k outputs output resistance high r oh iout = ?10 ma 0.4 0.8 output resistance low r ol iout = +10 ma 0.4 0.8 peak source current (2) i source out = gnd 200 ns pulse 10 a miller plateau source current (2) i source out = 5.0 v 200 ns pulse 7 a peak sink current (2) i sink out = vdd 200 ns pulse 10 a miller plateau sink current (2) i sink out = 5.0 v 200 ns pulse 7 a
ncp81074a, ncp81074b www. onsemi.com 5 table 2. electrical characteristics (note 1) (typical values: v dd =12v, 1uf from vdd to gnd,ta = tj = ?40 c to 140 c, typical at t amb = 25 c, unless otherwise specified) parameter unit max typ min test conditions symbol switching characteristics propagation delay time low to high, in rising (in to out) (note 2) t d1 c load = 1.8 nf 15 27 ns propagation delay time high to low, in falling (in to out) (note 2) t d2 c load = 1.8 nf 15 27 ns rise time (note 2) t r c load = 1.8 nf 4 7 ns fall time (note 2) t f c load = 1.8 nf 4 7 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. all limits are 100% tested at tamb = 25 c and guaranteed across temperature by design and statistical analysis. 2. guaranteed by characterization. *see timing waveforms. table 3. logic truth table in+ in? outh outl out (outh & outl connected together) l l high?z l l l h high?z l l h l h high?z h h h high?z l l figure 3. non?inverting input driver operation figure 4. inverting input driver operation
ncp81074a, ncp81074b www. onsemi.com 6 typical characteristics figure 5. supply current vs. switching frequency, v dd = 12 v figure 6. supply current vs. switching frequency, v dd = 4.5 v switching frequency (khz) switching frequency (khz) 2000 1400 1200 1000 800 600 200 0 0 50 100 150 200 250 200 0 1400 1200 1000 800 400 200 0 0 10 30 40 60 70 90 100 figure 7. fall time vs. temperature c load = 1.8 nf figure 8. rise time vs. temperature c load = 1.8 nf temperature ( c) temperature ( c) 140 100 80 60 0 ?20 ?40 ?60 3.00 3.25 3.50 3.75 4.25 4.50 4.75 5.00 16 0 140 80 60 40 0 ?20 ?60 4.0 7.0 5.0 5.5 6.0 7.5 8.0 figure 9. propagation delay t d1 vs. supply voltage figure 10. propagation delay t d2 vs. supply voltage v dd , supply voltage (v) v dd , supply voltage (v) 20 16 14 12 10 8 6 4 10 11 12 13 14 16 17 18 20 18 14 12 10 8 6 4 7 8 10 11 12 13 15 16 supply current (ma) supply current (ma) fall time (ns) rise time (ns) t d1 , delay time (ns) t d2 , delay time (ns) 400 1800 1600 600 1600 1800 20 50 80 10 nf 4.7 nf 2.2 nf 470 pf 1 nf 10 nf 4.7 nf 2.2 nf 470 pf 1 nf 20 40 120 160 4.00 20 v 15 v 5 v 10 v 120 100 20 ?40 20 v 15 v 5 v 10 v 4.5 6.5 18 15 c load = 1 nf c load = 2.2 nf c load = 4.7 nf c load = 10 nf c load = 1 nf c load = 2.2 nf c load = 4.7 nf c load = 10 nf 16 9 14
ncp81074a, ncp81074b www. onsemi.com 7 typical characteristics figure 11. supply current vs. supply voltage c load = 2.2 nf figure 12. supply current vs. supply voltage c load = 4.7 nf supply voltage (v) supply voltage (v) 20 18 16 14 10 8 6 4 0 20 60 80 120 140 180 200 20 16 14 12 10 8 6 4 0 20 60 80 120 140 180 200 figure 13. reverse current, p mos(on) , p mos(off) figure 14. reverse current, p mos(off) , p mos(on) out h ? vdd (v) out l (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 0 2 4 6 8 12 14 16 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 0 2 6 8 10 14 18 20 figure 15. supply current vs. supply voltage supply voltage (v) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 supply current (ma) supply current (ma) output current (a) output current (a) supply current (a) 12 40 100 160 18 40 100 160 2 mhz 1 mhz 10 test conditions: t j = 25 c 1 s positive pulse fsw = 1 khz test conditions: t j = 25 c 1 s positive pulse fsw = 1 khz 4 12 16 1.2 in? = vdd in+ = vdd gnd and vdd
ncp81074a, ncp81074b www. onsemi.com 8 bench waveforms ? non?inverting input figure 16. rise time with 1.8 nf load figure 17. fall time with 1.8 nf load figure 18. propagation delays with 1.8 nf load figure 19. propagation delays with 1.8 nf load
ncp81074a, ncp81074b www. onsemi.com 9 bench waveforms ? inverting input figure 20. rise time with 1.8 nf load figure 21. fall time with 1.8 nf load figure 22. propagation delays with 1.8 nf load figure 23. propagation delays with 1.8 nf load
ncp81074a, ncp81074b www. onsemi.com 10 pcb layout recommendation proper component placement is extremely important in high current, fast switching applications to provide appropriate device operation and design robustness. the ncp81074 gate driver exhibits a powerful output stage enabling large peak currents with fast rise and fall times. eventhough the ncp81074 provides a split output configuration for slew rate control, a proper pcb layout is crucial to ensure maximum performance. the following circuit layout guidelines are strongly recommended when designing with the ncp81074. ? place the driver close to the power mosfet in order to have a low impedance path between the output pins and the gate. keep the traces short and wide to minimize the parasitic inductance and accommodate for high peak currents. ? place the decoupling capacitor close to the gate drive ic. placing the vdd capacitor close to the pin and ground improves noise filtering. this capacitor supplies high peak currents during the turn?on transition of the mosfet. using a low esl chip capacitor is highly recommended. ? keep a tight turn?on turn?off current loop paths to minimize parastic inductance. high di/dt will induce voltage spikes on the output pin and the mosfet gate. parallel the source and return signals taking advantage of flux cancellation. ? since the ncp81074 is a 2x2mm package driving high peak currents into capacitive loads, adding a shielding ground plane helps in power dissipation and noise blocking. the ground plane should not be a current carrying path to any of the current loops. ? any unused pin, should be pulled to either rail depending on the functionality of the pin to avoid any malfunction on the output. please refer to the pin description table for more information. figure 24.
ncp81074a, ncp81074b www. onsemi.com 11 package dimensions dfn8 2x2 case 506aa issue e ?? ?? a d e b c 0.15 pin one 2x reference 2x top view side view bottom view a l (a3) d2 e2 c c 0.15 c 0.10 c 0.08 note 4 a1 seating plane e/2 e 8x k note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.20 0.30 d 2.00 bsc d2 1.10 1.30 e 2.00 bsc e2 0.70 0.90 e 0.50 bsc k l 0.25 0.35 1 4 8 5 l1 detail a l optional constructions l ??? 0.10 0.30 ref *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.50 8x dimensions: millimeters 0.30 pitch 8x 1 package outline recommended 0.90 1.30
ncp81074a, ncp81074b www. onsemi.com 12 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81074/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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